Samsung Electronics Unveils 400-Layer BV-NAND and zHBM Concepts

Samsung Electronics has unveiled the 400-layer BV-NAND design and the zHBM concept, which stacks memory on top of AI accelerators. This initiative focuses on reducing data movement distances to alleviate memory and storage bottlenecks in AI systems. Samsung introduced the V10 Bonding V-NAND design at the Future of Memory and Storage 2026 event held in Santa Clara, California, from the 5th to the 7th. BV-NAND is designed to increase storage density by approximately 58% and enhance performance through wafer bonding techniques. Wafer bonding combines a wafer with memory cells and a wafer containing surrounding circuits, emphasizing the need for high capacity and power efficiency required by AI systems. Samsung also presented the concepts of zHBM and zNAND-O, with zHBM featuring a structure that vertically stacks memory over accelerators to reduce data transfer distances. According to the disclosed information, zHBM aims for over 10 times the storage density compared to existing HBM5 and about three times the energy efficiency. This announcement indicates that the competition in HBM is expanding into packaging, foundry, and memory integration. The event will focus on memory and storage technologies for AI systems and data centers as key agenda items.

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